Power converter

ABSTRACT

The present description concerns a power converter (400) comprising: a switch (114) comprising first (114d) and second (114s) conduction terminals intended to receive a first AC voltage (Vds), a first circuit (402) for detecting a minimum value reached by the first voltage at each halfwave, and for averaging minimum values over a plurality of halfwaves, and a second circuit (404) for controlling the switch configured, according to the average of said values, to turn on the switch when the first voltage is substantially null.

FIELD

The present disclosure generally concerns electronic devices. Thepresent disclosure more specifically concerns power converters.

BACKGROUND

Among existing power converters, inverters enabling to convert a DCinput voltage into an AC output voltage are for example known. Existinginverters however exhibit operating drifts particularly linked toambient condition variations and to aging phenomena.

SUMMARY

There is a need to improve known power converters.

An embodiment overcomes all or part of the disadvantages of known powerconverters.

An embodiment provides a power converter comprising:

-   -   a switch comprising first and second conduction terminals        intended to receive a first AC voltage;    -   a first circuit for detecting a minimum value reached by the        first voltage at each halfwave, and for averaging minimum values        over a plurality of halfwaves; and    -   a second circuit for controlling the switch configured,        according to the average of said values, to turn on the switch        when the first voltage is substantially null.

According to an embodiment, the first circuit has a time constant atleast five times greater, preferably at least ten times greater, than aperiod of the first voltage.

According to an embodiment, the first circuit comprises, between a firstnode coupled, preferably connected, to the first conduction terminal ofthe switch and a second node of application of a reference potential, ahalfwave rectification element in series with a parallel association ofa capacitive element and of a resistor.

According to an embodiment, a third node, located between the halfwaverectifying element and the parallel association of the capacitiveelement and of the resistor, exhibits a potential which is a function ofa lower envelope of the first voltage.

According to an embodiment, the halfwave rectification element is adiode.

According to an embodiment, the first circuit further comprises a sourceof a voltage coupled, preferably connected, between the parallelassociation of the capacitive element and of the resistor and the secondnode.

According to an embodiment, the second circuit is further configured tomodify a duty cycle of the switch according to the average of saidvalues.

According to an embodiment, the switch is a field-effect transistor, thefirst and second terminals respectively corresponding to drain andsource terminals of the transistor.

According to an embodiment, the switch has a switching frequency in therange from 0.1 MHz to 100 MHz, preferably in the range from 1 to 10 MHz,more preferably equal to approximately 1.5 MHz.

According to an embodiment, the converter further comprises apiezoelectric resonator adapted to delivering the first voltage.

According to an embodiment, the second circuit comprises:

-   -   a comparator of the average of said values with a threshold;    -   a corrector; and    -   a pulse-width modulation circuit.

According to an embodiment, the threshold is a function of a powerconsumption of a load powered by the converter.

An embodiment provides a method of controlling a power converter such asdescribed, comprising the steps of:

a) averaging the minimum values of the first AC voltage after aplurality of halfwaves; andb) adjusting a turn-on time of the switch according to the average ofsaid values.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing features and advantages, as well as others, will bedescribed in detail in the rest of the disclosure of specificembodiments given by way of illustration and not limitation withreference to the accompanying drawings, in which:

FIG. 1 partially and schematically shows an example of a powerconverter;

FIG. 2 is a graph of an example of variation of a voltage across aswitch of the converter of FIG. 1 ;

FIG. 3 is a graph of another example of variation of the voltage acrossthe switch of the converter of FIG. 1 ;

FIG. 4 partially and schematically shows a power converter according toa first embodiment;

FIG. 5 partially and schematically shows a variant of the converter ofFIG. 4 ;

FIG. 6 partially and schematically shows a variant of a circuit of theconverter of FIG. 4 ;

FIG. 7 partially and schematically shows another variant of a circuit ofthe converter of FIG. 4 ;

FIG. 8 partially and schematically shows a portion of a power converteraccording to a second embodiment;

FIG. 9 partially and schematically shows a variant of the portion of theconverter of FIG. 8 ;

FIG. 10 is a graph of the variation of a potential of the converter ofFIG. 4 according to a duty cycle of a switch; and

FIG. 11 is a graph of the variation of an efficiency of the convertersof FIGS. 1 and 4 according to an inductance of an inductive element ofthese converters.

DETAILED DESCRIPTION OF THE PRESENT EMBODIMENTS

Like features have been designated by like references in the variousfigures. In particular, the structural and/or functional features thatare common among the various embodiments may have the same referencesand may dispose identical structural, dimensional and materialproperties.

For the sake of clarity, only the steps and elements that are useful foran understanding of the embodiments described herein have beenillustrated and described in detail. In particular, the applicationsusing the power converters are not detailed, the described embodimentsbeing compatible with usual applications implementing power converters.

Unless indicated otherwise, when reference is made to two elementsconnected together, this signifies a direct connection without anyintermediate elements other than conductors, and when reference is madeto two elements coupled together, this signifies that these two elementscan be connected or they can be coupled via one or more other elements.

In the following disclosure, unless otherwise specified, when referenceis made to absolute positional qualifiers, such as the terms “front”,“back”, “top”, “bottom”, “left”, “right”, etc., or to relativepositional qualifiers, such as the terms “above”, “below”, “upper”,“lower”, etc., or to qualifiers of orientation, such as “horizontal”,“vertical”, etc., reference is made to the orientation shown in thefigures.

Unless specified otherwise, the expressions “around”, “approximately”,“substantially” and “in the order of” signify within 10%, and preferablywithin 5%.

FIG. 1 partially and schematically shows an example of a power converter100. The converter 100 illustrated in FIG. 1 is more precisely aninverter of L-piezo type.

In the shown example, converter 100 comprises a source 102 fordelivering a DC voltage Vin. Source 102 comprises a negative terminal(−) coupled, preferably connected, to a node 104, or a rail, ofapplication of a reference potential, for example, the ground. Source102 further comprises another positive terminal (+) coupled, preferablyconnected, to another node 106.

A first inductive element 108 of inductance Lf, for example, a coil,couples, preferably connects, node 106 to still another node 110 ofconverter 100.

In the shown example, converter 100 comprises a piezoelectric element112 (typically a resonator) coupling, preferably connecting, nodes 110and 104.

A switch 114 couples, preferably connects, nodes 110 and 104. Switch 114is for example a field-effect power transistor (FET), for example, a MOS(Metal-Oxide-Semiconductor) transistor. Switch 114 is preferably anN-channel MOS transistor, or NMOS transistor.

As a variant, the switch is a high electron mobility transistor (HEMT).In this case, transistor 114 is preferably a HEMT transistor based ongallium nitride (GaN).

Switch 114 comprises a first conduction terminal 114 d (drain) coupled,preferably connected, to node 110 and another conduction terminal 114 s(source) coupled, preferably connected, to node 104. Switch 114 furthercomprises a third control terminal 114 g (gate).

As an example, the switch 114 of converter 100 has a switching frequency(set by a control circuit, not shown) in the range from 0.1 MHz to 100MHz, preferably in the range from 1 to 10 MHz, more preferably equal toapproximately 1.5 MHz.

The periodic switching of switch 114 causes the generation, bypiezoelectric element 112, of an oscillating signal, for example, aperiodic sinusoidal signal. In the shown example, an AC voltage Vds ispresent between the drain and source terminals 114 d and 114 s oftransistor 114.

In the case of an NMOS transistor, transistor 114 is in an on state whena voltage Vgs greater than or equal to a threshold voltage Vth1 isapplied between its gate terminal 114 g and its source terminal 114 sand in an off state when voltage Vgs is lower than threshold voltageVth1.

In the shown example, power converter 100 further comprises a secondinductive element 116 of inductance Ls, for example, a coil, in serieswith a capacitive element 120 of capacitance Cs, for example, acapacitor, between terminal 110 and an output terminal 122 of theconverter.

A load, for example, resistive, symbolized in FIG. 1 by a resistor 124of value Rout, is intended to be coupled, preferably connected, betweenoutput terminal 122 and node 104 of application of the referencepotential.

In operation, source 102 applies DC voltage Vin between the nodes 106and 104 of converter 100. Transistor 114 applies, between nodes 110 and104, AC voltage Vds, which results in having piezoelectric element 112oscillate. AC voltage Vds is filtered by this element 112, by secondinductive element 116, and by capacitive element 120, before beingapplied across load 124. Typically, the LC filter formed by elements 116and 120 enables to ascertain that the voltage Vout generated betweennodes 122 and 104 is a sinusoidal voltage corresponding to voltage Vds,at least only one fundamental component of which is kept.

More precisely, transistor 114 is typically controlled in pulse-widthmodulation (PWM) to generate AC voltage Vds which is particularlyfiltered by piezoelectric element 112 to obtain the desired voltage Vds.The switching frequency of transistor 114 is substantially constant andequal to half the oscillation frequency of piezoelectric resonator 112.After each switching from the off state to the on state, transistor 114is maintained all the longer in the on state as the power required byload 124 is high. Conversely, switch 114 is for example maintained allthe shorter in the on state as the power required by load 124 is low.

FIG. 2 is a graph of an example of variation, according to time t, ofthe voltage Vds across the transistor 114 of the converter 100 of FIG. 1. FIG. 2 more precisely illustrates an example of a shape of a positivehalfwave of voltage Vds.

In the shown example, transistor 114 is turned on at a time t_close andthen turned off at a time t_open. From time t_open, a voltage appearsbetween the first and second conduction terminals 114 d, 114 s oftransistor 114. Little before the turn-off time t_close of transistor114 (box 202), voltage Vds becomes negative. This causes the flowing ofa low current in a reverse diode of transistor 114. At time t_close,voltage Vds becomes zero and the flowing of the current between thefirst and second conduction terminals 114 d, 114 s of transistor 114 isthen interrupted.

Time t_close approximately corresponds to a time when the voltage Vgsapplied between the gate and source terminals 114 g and 114 s oftransistor 114 becomes greater than or equal to the threshold voltageVth1 of this transistor. At time t_close, transistor 114 then becomessubstantially conducting. Time t_open approximately corresponds to atime when voltage Vgs becomes strictly smaller than threshold voltageVth1. At time t_open, transistor 114 then becomes substantiallynon-conducting.

At a time t_null, prior to the turn-on time t_close of transistor 114(box 202) and close to time t_close, the voltage Vds between the nodes110 and 104 of converter 100 is substantially null. At time t_close,voltage Vds is for example in the range from −0.1 to −2 V. In theexample illustrated in FIG. 2 , voltage Vds is more precisely equal toapproximately −2 V at time t_close.

The example shown in FIG. 2 , where transistor 114 is on when voltageVds is negative and close to 0 V, corresponds to a case called quasizero voltage switching or quasi ZVS. In this case, the switching causesfew disturbances of converter 100 and generates low power losses at thelevel of transistor 114.

FIG. 3 is a graph of another example of variation of the voltage Vdsacross the transistor 114 of the converter 100 of FIG. 1 . FIG. 3 moreprecisely illustrates an example of shape of another positive halfwaveof AC voltage Vds.

In the shown example, in the vicinity of the turn-on time t_close oftransistor 114 (box 302), the voltage Vds between the nodes 110 and 104of converter 100 is positive. At time t_close, voltage Vds is forexample in the range from 0.5 to 5 V. In the example illustrated in FIG.3 , voltage Vds is more precisely equal to approximately 4 V at timet_close.

The example shown in FIG. 3 , where transistor 114 is on when voltageVds is positive and for example equal to several volts, corresponds to acase called hard switching, or abrupt switching. In this case, theswitching causes strong disturbances of converter 100 and generatessignificant power losses at the level of transistor 114. More precisely,in the example illustrated in FIG. 3 , the hard switching causes justafter time t_close a very fast variation dVs/dt of the voltage Vdsacross transistor 114. This results in a strong current peak intransistor 114, capable of causing an irreversible damage of thistransistor.

Accordingly, it is generally desired to avoid abrupt switchings of thetype of that illustrated in FIG. 3 and switchings of quasi-ZVS type arerather preferred, as discussed hereabove in relation with FIG. 2 . Forthis purpose, converter 100 is initially set so that the switching attime t_close is performed in quasi ZVS by adjusting control parametersof transistor 114. Due in particular to variations of the power consumedby load 124 and to variations of physical characteristics of elements ofconverter 100 (for example, fluctuations of the value of inductance Lfand of the resonance frequency of piezoelectric resonator 112), it ishowever difficult to maintain an operation of this type.

Typically, manufacturing tolerances of the elements of converter 100,ambient temperature variations, a phenomenon of aging of the elements,etc. cause little by little a drift in the operation resulting in a lossof the quasi-ZVS switching.

To overcome this problem, a pulse disturbance detection circuit, forexample, a circuit for detecting the voltage slope analog to the circuitdisclosed in S. Li, W. Shu, and S. Lu's publication, entitled “Voltageslope-based zero voltage switching detection method for wireless powertransfer systems” (Electron. Lett., vol. 54, no 12, p. 775 777, 2018)could have been provided. However, such a circuit would not be adaptableto a converter of the type of the converter 100 of FIG. 1 comprising asingle switch 114. Further, the circuit described in the above-mentionedpublication requires the use of active elements or components intendedto reset detection information at each period. This causes an additionalelectric power consumption, correspondingly decreasing the powerefficiency of the converter.

A circuit of detection by source voltage sampling, for example, similarto the circuit described in U.S. Pat. No. 5,166,549, could also havebeen provided. Such a circuit for example takes advantage of a resistorassociated in series with a power converter to detect a switching in thevicinity of the voltage zero of this switch. This however requiresadding an element, in the case in point a resistor, inside of the powerloop of the converter. This resistor disadvantageously generates anincrease in the power losses of the converter, and thus adverselyaffects its efficiency.

FIG. 4 schematically and partially shows a power converter 400 accordingto an embodiment. The converter 400 of FIG. 4 comprises elements commonwith the converter 100 of FIG. 1 . These common elements will not bedescribed again hereafter.

The converter 400 of FIG. 4 differs from the converter 100 of FIG. 1mainly in that converter 400 further comprises a first detection circuit402 and a second control circuit 404.

According to an embodiment, first circuit 402 is a circuit for detectinga minimum value reached by AC voltage Vds at each halfwave and foraveraging of this minimum value over a plurality of halfwaves of thisvoltage.

In the shown example, circuit 402 comprises a halfwave rectificationelement 406. Halfwave rectification element 406 is for example, asillustrated in FIG. 4 , a diode having an anode coupled, preferablyconnected, to a node 408 of circuit 402 and having a cathode coupled,preferably connected, to a node 408 of circuit 402 and having a cathodecoupled, preferably connected, to the node 110 of converter 400. Diode406 is conducting when the voltage Vak between its anode and its cathodeis greater than or equal to a threshold voltage Vth2 of this diode andis otherwise non-conducting. For simplification, it is assumed thatdiode 406 is never submitted to a reverse bias voltage sufficiently highto have it enter the avalanche state. As an example, the thresholdvoltage Vth2 of diode 406 is in the range from 0.2 to 0.7 V, forexample, equal to approximately 0.6 V for a silicon diode.

In the rest of the disclosure, note Vα the potential present at node408.

In the shown example, circuit 402 further comprises a resistor 410, ofvalue R1, associated in parallel with another capacitive element 412,for example, a capacitor of capacitance C1. Resistor 410 comprises aterminal coupled, preferably connected, to node 408 and another terminalcoupled, preferably connected, to the node 104 of application of thereference potential. Similarly, capacitive element 412 comprises aterminal coupled, preferably connected, to node 408 and another terminalcoupled, preferably connected, to node 104. Resistor 410 may be made inthe form of a MOS transistor biased as a current source.

The role of RC cell 410-412 is to average, over a plurality of halfwavesof voltage Vds, the minimum value that it reaches.

The role of diode 406 is to conduct an electric current between nodes110 and 408 when voltage Vds is smaller than or equal to potential Vαminus a voltage drop across this diode. This then causes a decrease inthe voltage across capacitor 412. However, diode 406 prevents anyflowing of a current between nodes 110 and 408 when voltage Vds isgreater than potential Vα plus the voltage drop across this diode.

During a halfwave of voltage Vds, voltage Vds increases for example fromthe turn-off time t_open of transistor 114, and then decreases in thevicinity of the turn-on time t_close of this transistor. It is assumed,as previously discussed in relation with FIG. 2 , that voltage Vds isnegative at time t_close. If voltage Vds further has a valuesufficiently low for the voltage Vak across diode 406 to be greater thanor equal to its threshold voltage Vth2, diode 406 is then conducting.This tends to charge node 408, and thus to decrease the potential Vαpresent at this node. This decrease is all the faster as voltage Vds islow. Thus, the higher the value of voltage Vds, the higher potential Vα.

Functionally, the first circuit 402 of converter 400 acts as a detectorof the lower envelope of voltage Vds.

During a next halfwave of voltage Vds, the increase of voltage Vds fromthe turn-off time t_open of transistor 114 causes a blocking of diode406. Node 408 is then isolated from node 110. This thus causes adischarge of node 408 to the node 104 of application of the referencepotential, and thus a decrease in potential Vα. This decrease ofpotential Vα is however damped or filtered, on successive halfwaves ofvoltage Vds, by the parallel association of resistor 410 and ofcapacitor 412.

Resistor R1 and capacitor C1 are for example such that first circuit 402has a time constant τ, equal in this example to the product of resistorR1 by capacitor C1 (τ=R1*C1), at least five times greater, for exampleat least ten times greater, than a period of AC voltage Vds. This thusenables to average, or smooth, values taken by potential Vα over aplurality of halfwaves of voltage Vds. Potential Vα is for exampleapplied to an input of second circuit 404. As an example, if theswitching frequency of transistor 114 is approximately equal to 10 MHz,time constant τ is in the order of one microsecond.

According to an embodiment, second circuit 404 is a circuit forcontrolling transistor 114 configured, according to the average of thevalues of potential Vα, to control the turning on of transistor 114 whenvoltage Vds is substantially null. Circuit 404 enables to ascertain thatthe turn-on time t_close of transistor 114 intervenes when voltage Vdsis, for example, in the range from 0 to −1 V.

Generally, the average of the values of potential Vα enables to estimatewhether converter 400 is in the quasi-ZVS operating mode, which isdesired to be maintained, or whether it approaches the hard switchingoperating mode, which is desired to be avoided. Second circuit 404 isconfigured to maintain converter 400 in the quasi-ZVS operating modewhere the switching (time t_close) is performed when voltage Vds isnegative and close to the voltage zero, despite drifts and the aging ofthe components of the converter.

In the shown example, circuit 404 comprises a comparator 414. Comparator414 for example comprises an input (+) coupled, preferably connected, tothe node 408 of circuit 402 and receiving potential Vα. Comparator 414for example comprises another input (−) of comparison with a threshold,the other input for example receiving a reference potential Vref. Thisother input of the comparator is for example coupled to a node, notshown, of application of reference potential Vref. Reference potentialVref is adjusted to obtain a quasi-ZVS operation. In the shown example,the value of potential Vref is equal to approximately 0.1 V.

In the shown example, an output of comparator 414 is connected to aninput of a corrector 416 (CORR). The comparator output for exampletransmits to the input of corrector 416 a signal which is an image of adifference of potential Vα with respect to reference signal Vref. As anexample, corrector 416 is a proportional integral (PI) regulator.Corrector 416 for example enables to obtain a regulation loop morestable than if circuit 404 comprised no corrector.

In this example, corrector 416 outputs a signal a. Signal a for examplecorresponds to a DC voltage which is an image of a duty cycle to beapplied to the transistor after the pulse-width modulation. Forsimplification, signal a will be designated with the term “duty cycle”in the rest of the disclosure.

In the shown example, the signal a at the output of corrector 416 istransmitted to an input of a pulse-width modulation (PWM) circuit 418.Circuit 418 is for example adapted to adjusting the turn-on and turn-offtimes t_close and t_open of transistor 114 according to signal a. Moreprecisely, in the shown example, the output of circuit 418 is connectedto the gate 114 g of transistor 114 and delivers signal Vgs to gate 114g.

Generally, first and second circuits 402, 404 enable to estimate,according to the average of the values of potential Vα, a difference inthe operation of converter 400 with respect to an operation wheretransistor 114 is off when voltage Vds is negative and close to 0 V(“quasi ZVS” operation). Circuits 402 and 404 further enable to adjustduty cycle a according to this difference to maintain the quasi-ZVSoperation of converter 400.

An advantage of converter 400 lies in the fact that it is capable ofcompensating for drifts, for example, inductance variations Lf of coil108 and fluctuations of the resonance frequency of resonator 112 overtime. This advantageously enables converter 400 to have a greater powerefficiency than the converter 100 of FIG. 1 , as well as an increasedlifetime.

Another advantage of converter 400 lies in the fact that circuit 404 forregulating the duty cycle a of transistors 114 allows modifications ofthe output power of this converter while maintaining the switching oftransistor 114 to the off state when voltage Vds is negative and closeto zero. As an example, for a 1.4-MHz frequency under 20 V, converter400 is capable of maintaining a quasi-ZVS operation over a power rangebetween 0 and 24 W, to be compared with between 9 and 21 W for theinverter 100 of FIG. 1 .

Still another advantage of converter 400 lies in the fact that itexhibits no power dissipation at the level of the power circuit.Further, converter 400 undergoes no degradation of the control of MOStransistor 114.

As a variant, diode 406 and the parallel association of resistor 410 andof capacitor 412 may be interchanged. In this case, diode 406 moreprecisely has its anode coupled, preferably connected, to node 104 ofapplication of the reference potential and its cathode coupled, to node408. Resistor 410 and capacitor 412 then each have a terminal coupled,preferably connected, to node 408 and another terminal coupled,preferably connected, to node 110.

FIG. 5 partially and schematically shows a variant of the converter 400of FIG. 4 . The circuit 404 of converter 400 has not been shown in FIG.5 to avoid overloading the drawing.

The variant illustrated in FIG. 5 differs from the embodimentillustrated in FIG. 4 mainly in that, in this variant, the first circuit402 of converter 400 further comprises a source 502 of a substantiallyconstant DC voltage Vpol. Source 502 is for example coupled, preferablyconnected, between node 104 of application of the reference potentialand the parallel association of resistor 410 and of capacitor 412.Source 502 more precisely comprises a negative terminal (−) coupled,preferably connected, to node 104 and another positive terminal (+)coupled, preferably connected, to a node 504 of circuit 402.

Bias voltage Vpol is approximately equal to the threshold voltage Vth2of diode 406. Advantage is thus taken of source 502 to compensate forthe threshold voltage Vth2 of diode 406. This enables to still moreeasily couple potential Vα to the lower envelope of AC voltage Vds toestimate whether converter 400 is in the quasi-ZVS operating mode orwhether it diverges therefrom.

FIG. 6 partially and schematically shows a variant of the circuit 402 ofthe converter 400 of FIG. 4 .

In this variant, the diode 406 of circuit 402 is replaced with a bipolartransistor 602, of PNP type. Transistor 602 is for example connected toobtain a function similar to that of diode 406. More precisely, in theshown example, transistor 602 comprises a first conduction terminal 602c (collector) coupled, preferably connected, to the node 104 ofapplication of the reference potential, a second conduction terminal 602e (emitter) coupled, preferably connected, to node 408, and a thirdcontrol terminal 602 b (base) coupled, preferably connected, to thedrain terminal 114 d of transistor 114.

Further, in this variant, the parallel association of resistor 410 andof capacitor 412 is not connected between node 408 and node 104 butbetween node 408 and another node 604, or a rail, of application of apower supply potential Vdd of circuit 402. As an example, potential Vddis substantially constant and in the range from 2 to 5 V, for example,equal to approximately 3 V.

The gain of transistor 602 is selected to be at least 50, so thatcollector current ic is much higher (by a ratio of at least 50) than thebase current ib drawn by transistor 114 when the latter is on (the sumof the base and collector currents being, for a PNP-type transistor,equal to the emitter current sampled from node 408).

The role of transistor 602 is to avoid for charges/discharges ofcapacitor 412 to disturb the operation of transistor 114.

The variant of circuit 402 discussed in relation with FIG. 6 has anoperation similar to that of the circuit 402 of FIG. 4 . The variant ofFIG. 6 however enables the capacitance C1 of capacitor 412 to be higherthan in the case of the embodiment of FIG. 4 , which enables to decreasevoltage drifts linked to leakage currents.

FIG. 7 partially and schematically shows another variant of the circuit402 of the converter 400 of FIG. 4 .

The variant of circuit 402 illustrated in FIG. 7 differs from thevariant of circuit 402 illustrated in FIG. 6 in that circuit 402 furthercomprises another halfwave rectification element 702. Halfwaverectification element 702 is for example a diode or a zener diode havingan anode coupled, preferably connected, to the base terminal 602 b ofbipolar transistor 602 and having a cathode coupled, preferablyconnected, to the drain terminal 114 d of power transistor 114.

Diode 702 advantageously enables to avoid for transistor 602 to beforced to withstand, between its terminals 602 b and 602 e, asignificant reverse voltage Vbe when transistor 114 is off. Anotheradvantage of this variant lies in the fact that diode 702 enables toincrease potential Vα and to ascertain that this potential is in avoltage range higher than for the variant of FIG. 6 . As an example,potential Vα is in this case in the range from 0 V to Vdd. It is thusavoided for potential Vα to be negative, which eases the regulation bysecond circuit 404.

Although this has not been shown in FIGS. 6 and 7 , potential Vα is forexample transmitted to second circuit 404 to adapt the control oftransistor 114 as previously discussed in relation with FIG. 4 .

FIG. 8 partially and schematically shows a portion of a power converter800 according to an embodiment.

The converter 800 of FIG. 8 comprises elements common with the converter400 of FIG. 4 . These common elements will not be described againhereafter.

The converter 800 of FIG. 8 differs from the converter 400 of FIG. 4mainly in that converter 800 comprises, in addition to switch 114,another switch 802. Switch 802 is for example a MOS transistor, similarto switch 114.

The terminal 114 s of transistor 114 is coupled, preferably connected,to node 104 and the terminal 114 d of transistor 114 is coupled,preferably connected, to a node 804 of converter 800.

Transistor 802 has a first conduction terminal 802 s (source) coupled,preferably connected, to node 804 and a second conduction terminal 802 d(drain) coupled, preferably connected, to another node 806 of converter800. Potential Vin is present between nodes 806 and 104.

Diode 406 has its anode terminal coupled, preferably connected, to node804 and its cathode terminal coupled, preferably connected, to node 408.The parallel association of resistor 410 and of capacitor 412 iscoupled, preferably connected, between nodes 408 and 806.

In the shown example, the series association of transistors 802 and 114between nodes 806 and 104 forms part of a bridge arm of converter 800.

The potential Vα present at node 408 is a function of a peak potentialpresent on the source terminal 802 s of transistor 802. Although thishas not been shown in FIG. 8 , converter 800 preferably comprises aregulation circuit or loop similar to the circuit 404 discussed inrelation with FIG. 4 . The regulation circuit of converter 800 thenenables to maintain the peak potential present on terminal 802 s betweenvoltage Vin and a voltage equal to Vin plus an inverse voltage oftransistor 802, corresponding to a conduction voltage of a reverse diodeof this transistor. The peak voltage is greater and substantially equalto voltage Vin.

As a variant, a bias source may be interposed between the node 806 ofconverter 800 and the parallel association of resistor 410 and ofcapacitor 412. This voltage source provides advantages similar to thosediscussed in relation with FIG. 5 for the source 502 of voltage Vpol.

FIG. 9 partially and schematically shows a variant of the portion of theconverter 800 of FIG. 8 .

The variant illustrated in FIG. 9 differs from the embodimentillustrated in FIG. 8 mainly in that the first circuit 402 of converter800 further comprises another halfwave rectification element 902,another capacitor element 904 and, optionally, another resistor 906.

Halfwave rectification element 902 is a diode having an anode coupled,preferably connected, to a node 908 of converter 800 and having acathode coupled, preferably connected, to node 806. Diode 902 is forexample similar to diode 406.

Capacitive element 904 comprises a terminal coupled, preferablyconnected, to node 908 and another terminal coupled, preferablyconnected, to node 804. Capacitive element 904, having a capacitance C2,is for example a capacitor similar to capacitor 412.

Optional resistor 906, having a value R2, is associated in parallel withcapacitive element 904. Resistor 906 comprises a terminal coupled,preferably connected, to node 908 and another terminal coupled,preferably connected, to node 804.

Further, the anode of diode 406 is coupled, preferably connected, tonode 408 and the cathode of diode 406 is coupled, preferably connected,to node 908. In this example, the parallel association of resistor 410and of capacitor 412 is coupled, preferably connected, between nodes 408and 604.

Further, capacitor 412 is connected between node 408 and node 604. As avariant, capacitor 412 is connected between node 408 and another node ofapplication of a fixed potential, for example, the node 104 ofapplication of the reference potential.

The variant of the converter 800 illustrated in FIG. 9 advantageouslyenables to ascertain that potential Vα varies in a larger voltage rangethan for the converter 800 of FIG. 8 . Potential Vα is in this case inthe range for example from 0 V to Vdd.

In operation, when transistor 114 is on and when transistor 802 is off,node 804 is taken to a potential substantially equal to that of node104. Resistor 410 in parallel with capacitive element 412 forms a filterenabling, after a plurality of halfwaves, to store at node 408 a minimumvalue of a potential difference between nodes 604 and 408 (to withinvoltage drops in diode 406). If the capacitance C2 of capacitor 904 ismuch higher, for example from ten to one hundred times higher, than thecapacitance C1 of capacitor 412, a charge transfer between capacitors904 and 412 will have little influence on a potential difference acrosscapacitor 904. In this case, potential Vα will rapidly stabilize, thatis, after a few halfwaves only (less than 10 halfwaves).

However, if the capacitance C2 of capacitor 904 is much lower, forexample, between ten and one hundred times lower, than the capacitanceC1 of capacitor 412, a charge transfer between capacitors 904 and 412will have a high influence on the potential difference across capacitor904. In this case, potential Vα will stabilize slowly, that is, after alarge number of halfwaves (at least 10 halfwaves).

When transistor 114 is switched to the off state and transistor 802 hasnot switched to the on state yet, the source terminal 802 s oftransistor 802 exhibits a potential which increases, for example due toa LC resonance. This potential may for example exceed voltage Vin. Inthis case, capacitive element 904 stores the peak value of the potentialpresent on the source terminal 802 s of transistor 802 with respect topotential Vin, to within the voltage drops in diode 902.

In a case where optional resistor 906 is present, this resistor enablesto filter the voltage across capacitor 904 when transistor 114 turns on.High-frequency disturbances causes by the turning on of transistors 114are thus advantageously removed or decreased.

As a variant, each diode 406, 902 may be replaced with a zener diode.This particularly enables to adjust the range within which potential Vαvaries.

FIG. 10 is a graph 1000 of the variation of the potential Vα present atthe node 408 of converter 400 of FIG. 4 according to duty cycle a.

In the shown example, graph 1000 comprises a first region 1002 whereduty cycle a is in the range from approximately 0.25 to approximately0.30. First region 1002 corresponds to the quasi-ZVS operating mode,where converter 400 is maintained. In region 1002, potential Vαincreases with duty cycle a. By averaging the values of potential Vαover a plurality of halfwaves, duty cycle a can be adjusted as discussedin relation with FIG. 4 to approach a switching point 1004 at thevoltage zero. Point 1004 corresponds to a value of duty cycle a forwhich transistor 114 is turned on at the time t_close when voltage Vdsis null.

Graph 1000 further comprises a second region 1006 where duty cycle a isin the range from approximately 0.30 to approximately 0.35. Secondregion 1006 corresponds to the hard switching operating mode, thatconverter 400 is prevented from reaching due to the previously-describedcontrol.

Although this has not been shown in FIG. 10 , the variants of converter400 discussed in relation with FIGS. 5, 6, and 7 as well as theconverter 800 of FIGS. 8 and 9 for example exhibit potential variationsVα, according to duty cycle a, similar to what is illustrated in FIG. 10for the converter 400 of FIG. 4 , to within a vertical offset.

FIG. 11 is a graph 1100 of variation of an efficiency η (in percent, %)of the converters 100 and 400 of FIGS. 1 and 4 according to aninductance Lf (in nanohenries, nH) of an inductive element 108 of theseconverters.

FIG. 11 more precisely comprises a first curve 1102 illustrating thevariation of the efficiency η of converter 100 and a second converter1104 illustrating the variation of the efficiency η of converter 400. InFIG. 11 , if can be observed that the efficiency η of converter 400 issubstantially always greater than the efficiency 11 of converter 100. Inparticular, when inductance Lf is equal to approximately 500 nH, theefficiency η of converter 400 is equal to approximately 96.5%, to becompared with 92% for converter 100.

Although this has not been shown in FIG. 11 , the variants of converter400 discussed in relation with FIGS. 6 and 7 as well as the converter800 of FIGS. 8 and 9 exhibit variations of efficiency η, according toinductance Lf, similar to curve 1104.

Various embodiments and variants have been described. Those skilled inthe art will understand that certain features of these variousembodiments and variants may be combined, and other variants will occurto those skilled in the art. In particular, although examples ofapplication to piezoelectric resonator converters have been discussedhereabove, the described embodiments are not limited to this type ofconverter, and those skilled in the art are particularly capable ofadapting the described embodiments to converters of class E, E2, phi2,etc.

Finally, the practical implementation of the described embodiments andvariants is within the abilities of those skilled in the art based onthe functional indications given hereabove. In particular, the selectionof the values of inductances Lf and Ls, of resistors R1 and R2, ofcapacitive elements C1, C2, and Cs, etc. is within the abilities ofthose skilled in the art.

1. Power converter comprising: a switch comprising first and secondconduction terminals intended to receive a first AC voltage; a firstcircuit for detecting a minimum value reached by the first voltage ateach halfwave, and for averaging minimum values over a plurality ofhalfwaves; and a second circuit for controlling the switch configured,according to the average of said values, to turn on the switch when thefirst voltage is substantially null.
 2. Converter according to claim 1,wherein the first circuit has a time constant at least five timesgreater, preferably at least ten times greater, than a period of thefirst voltage.
 3. Converter according to claim 1, wherein the firstcircuit comprises, between a first node coupled, preferably connected,to the first conduction terminal of the switch and a second node ofapplication of a reference potential, a halfwave rectification elementin series with a parallel association of a capacitive element and of aresistor.
 4. Converter according to claim 3, wherein a third node,located between the halfwave rectification element and the parallelassociation of the capacitive element and of the resistor, exhibits apotential which is a function of a lower envelope of the first voltage.5. Converter according to claim 3, wherein the halfwave rectificationelement is a diode.
 6. Converter according to claim 3, wherein the firstcircuit further comprises a source of a voltage coupled, preferablyconnected, between the parallel association of the capacitive elementand of the resistor and the second node.
 7. Converter according to claim1, wherein the second circuit is further configured to modify a dutycycle of the switch according to the average of said values. 8.Converter according to claim 1, wherein the switch is a field-effecttransistor, the first and second terminals respectively corresponding todrain and source terminals of the transistor.
 9. Converter according toclaim 1, wherein the switch has a switching frequency in the range from0.1 MHz to 100 MHz, preferably in the range from 1 to 10 MHz, morepreferably equal to approximately 1.5 MHz.
 10. Converter according toclaim 1, further comprising a piezoelectric resonator adapted todelivering the first voltage.
 11. Converter according to claim 1,wherein the second circuit comprises: a comparator of the average ofsaid values with a threshold; a corrector; and a pulse-width modulationcircuit.
 12. Converter according to claim 11, wherein the threshold is afunction of a power consumption of a load powered by the converter. 13.A method of controlling the converter according to claim 1, the methodcomprising the following steps: a) averaging the minimum values of thefirst AC voltage after a plurality of halfwaves; and b) adjusting aturn-on time (t_close) of the switch according to the average of saidvalues.